View SSTVN16859BS_1317131.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
SSTVN16859 13-bit 1:2 SSTL_2 registered buffer for DDR
Product data sheet 2004 Jul 15
Philips Semiconductors
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
FEATURES
* Stub-series terminated logic for 2.5 V VDD (SSTL_2) * Designed for PC1600-PC2700 (at 2.5 V) and PC3200 (at 2.6 V)
applications
such as DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK going LOW. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the outputs will remain LOW.
* Pin and function compatible with JEDEC standard SSTV16859 * Supports SSTL_2 signal inputs as per JESD 8-9 * Flow-through architecture optimizes PCB layout * ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
* Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
* Supports efficient low power standby operation * Full DDR solution when used with PCKVF857 * Available in 56-terminal HVQFN packages
DESCRIPTION
The SSTVN16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V for PC1600 - PC2700 applications or between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTVN16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC,
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns SYMBOL tPHL/tPLH CI PARAMETER Propagation delay; CK to Qn Input capacitance CONDITIONS CL = 30 pF; VDD = 2.5 V VCC = 2.5 V TYPICAL 1.7 2.8 UNIT ns pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 56-Terminal Plastic HVQFN TEMPERATURE RANGE 0 C to +70 C ORDER CODE SSTVN16859BS DWG NUMBER SOT684-1
2004 Jul 15
2
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
56-TERMINAL CONFIGURATION
Q10A Q12A Q13A Q11A VDDQ VDDQ VDDQ GND Q8B Q9A VDDI D13 D12 D11
LOGIC DIAGRAM
RESET 51 16
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1D 42 D10 41 D9 40 39 38 D8 D7 RESET D1 VREF 35 45 CK CK 48 49 C1
Q1A
Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ
1 2 3 4 5 6 7 8 9
32 R
Q1B
37 GND 36 CK VDDQ VDDI VREF to 12 other channels
35 CK 34 33 32
SW00750
Q12B 10 Q11B 11 Q10B 12 Q9B 13 Q8B 14 Q7B 15 Q6B 16 VDDQ 17 Q5B 18 Q4B 19 Q3B 20 21 22 VDDQ 23 D1 24 D2 25 VDDI 26 27 D3 28
31 D6 30 D5 29 D4
FUNCTION TABLE (each flip flop)
INPUTS RESET H H CK L or H X or floating CK # # L or H X or floating D L H X X or floating OUTPUT Q L H Q0 L
Q2B
Q1B
VDDQ
SW01040
H L
TERMINAL DESCRIPTION
TERMINAL NUMBER 1, 2, 3, 4, 5, 6, 7, 50, 51, 52, 53, 54, 56 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22 9, 17, 23, 27, 34, 44, 49, 55 26, 33, 45 37, 48 24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47 32 35, 36 SYMBOL NAME AND FUNCTION
Q13A-Q1A
Data output
H = HIGH voltage level L = LOW voltage level = HIGH-to-LOW transition = LOW-to-HIGH transition X = Don't care
Q13B-Q1B
Data output
VDDQ VDDI GND
Power supply voltage Power supply voltage Ground Data input: clocked in on the crossing of the rising edge of CK and the falling edge of CK Input reference voltage Positive and negative master clock input Asynchronous reset input: resets registers and disables data and clock differential input receivers
D1-D13
VREF CK, CK
51
RESET
2004 Jul 15
3
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VDD VI VO IIK IOK IO PARAMETER Supply voltage range Input voltage range Output voltage range Input clamp current Output clamp current Continuous output current Continuous current through each VDD or GND Tstg Storage temperature range Notes 2 and 3 Notes 2 and 3 VI < 0 V or VI > VDD VO < 0 V or VO > VDD VO = 0 V to VDD CONDITION LIMITS MIN -0.5 -0.5 -0.5 -- -- -- -- -65 MAX +3.6 VDD + 0.5 VDD + 0.5 50 50 50 100 +150 UNIT V V V mA mA mA mA C
NOTES: 1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 3. This value is limited to 3.6 V maximum. 4. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C.
RECOMMENDED OPERATING CONDITIONS1
SYMBOL VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL Tamb PARAMETER Supply voltage Reference voltage g (VREF = VDD/2) Termination voltage Input voltage AC HIGH-level input voltage AC LOW-level input voltage DC HIGH-level input voltage DC LOW-level input voltage HIGH-level input voltage LOW-level input voltage Common-mode input range Differential input voltage HIGH-level output current LOW-level output current Operating free-air temperature range CK, CK CK, CK Data inputs Data inputs Data inputs Data inputs RESET PC1600-PC2700 PC3200 CONDITIONS MIN VDD 1.15 1.25 VREF - 40 mV 0 VREF + 310 mV -- VREF + 150 mV -- 1.7 0.0 0.97 360 -- -- 0 TYP -- 1.25 1.3 VREF -- -- -- -- -- -- -- -- -- -- -- -- MAX 2.7 1.35 1.35 VREF + 40 mV VDD -- VREF - 310 mV -- VREF - 150 mV VDD 0.7 1.53 -- -16 16 +70 UNIT V V V V V V V V V V V V mV mA mA C
NOTE: 1. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW.
2004 Jul 15
4
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
DC ELECTRICAL CHARACTERISTICS--PC1600-PC2700
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VIK VO OH VO OL II IDD All inputs Static standby Static operating Dynamic operating - clock only IDDD Dynamic operating - per each data input Data inputs Ci CK and CK RESET PARAMETER TEST CONDITIONS II = -18 mA, VDD = 2.3 V IOH = -100 A, VDD = 2.3 V to 2.7 V IOH = -16 mA, VDD = 2.3 V IOL = 100 A, VDD = 2.3 V to 2.7 V IOL = 16 mA, VDD = 2.3 V VI = VDD or GND, VDD = 2.7 V RESET = GND RESET = VDD, VI = VIH(AC) or VIL(AC) RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. VI = VREF 310 mV, VDD = 2.5 V VICR = 1.25 V, VI(PP) = 360 mV, VDD = 2.5 V VI = VDD or GND, VDD = 2.5 V IO = 0 mA; VDD = 2.7 V -- 9 -- IO = 0 mA; VDD = 2.7 V Tamb = 0 C to +70 C MIN -- VDD - 0.2 1.95 -- -- -- -- -- -- TYP -- -- -- -- -- -- -- -- 15 MAX -1.2 -- -- 0.2 0.35 5 0.01 45 -- mA V V V A UNIT
A/ clock MHz
A/ clock MHz/ data input
2.5 2.5 --
2.8 3.2 2.4
3.5 3.5 3.5 pF
2004 Jul 15
5
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
DC ELECTRICAL CHARACTERISTICS--PC3200
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VIK VO OH VO OL II IDD All inputs Static standby Static operating Dynamic operating - clock only IDDD Dynamic operating - per each data input Data inputs Ci CK and CK RESET PARAMETER TEST CONDITIONS II = -18 mA, VDD = 2.5 V IOH = -100 A, VDD = 2.5 to 2.7 V IOH = -16 mA, VDD = 2.5 V IOL = 100 A, VDD = 2.5 to 2.7 V IOL = 16 mA, VDD = 2.5 V VI = VDD or GND, VDD = 2.7 V RESET = GND RESET = VDD, VI = VIH(AC) or VIL(AC) RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. VI = VREF 310 mV, VDD = 2.6 V VICR = 1.25 V, VI(PP) = 360 mV, VDD = 2.6 V VI = VDD or GND, VDD = 2.6 V IO = 0 mA; VDD = 2.7 V -- 9 -- IO = 0 mA; VDD = 2.7 V Tamb = 0 C to +70 C MIN -- VDD - 0.2 1.95 -- -- -- -- -- -- TYP -- -- -- -- -- -- -- -- 15 MAX -1.2 -- -- 0.2 0.35 5 0.01 45 -- mA V V V A UNIT
A/ clock MHz
A/ clock MHz/ data input
2.5 2.5 --
2.8 3.2 2.4
3.5 3.5 3.5 pF
2004 Jul 15
6
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
TIMING REQUIREMENTS--PC1600-PC2700
Over recommended operating conditions; Tamb = 0 C to +70 C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VDD = 2.5 V 0.2 V MIN fclock tw tact tinact Clock frequency Pulse duration, CK, CK HIGH or LOW Differential inputs active time Differential inputs inactive time Setup time, fast slew rate (see Notes 4 and 6) Setup time, slow slew rate (see Notes 5 and 6) Hold time, fast slew rate (see Notes 4 and 6) Hold time, slow slew rate (see Notes 5 and 6) Notes 1, 2 Notes 1, 3 -- 2.5 -- -- 0.65 Data before CK, CK CK 0.75 0.75 Data after CK, CK CK 0.9 ns ns MAX 200 -- 22 22 MHz ns ns ns UNIT
tsu
th
NOTES: 1. This parameter is not necessarily production tested. 2. Data inputs must be below a minimum time of tact max, after RESET is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken LOW. 4. For data signal input slew rate 1 V/ns. 5. For data signal input slew rate 0.5 V/ns and < 1 V/ns. 6. CK, CK signals input slew rates are 1 V/ns.
TIMING REQUIREMENTS--PC3200
Over recommended operating conditions; Tamb = 0 C to +70 C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VDD = 2.6 V 0.1 V MIN fclock tw tact tinact Clock frequency Pulse duration, CK, CK HIGH or LOW Differential inputs active time Differential inputs inactive time Setup time, fast slew rate (see Notes 4 and 6) Setup time, slow slew rate (see Notes 5 and 6) Hold time, fast slew rate (see Notes 4 and 6) Hold time, slow slew rate (see Notes 5 and 6) Notes 1, 2 Notes 1, 3 -- 2.5 -- -- 0.65 Data before CK, CK CK 0.75 0.65 Data after CK, CK CK 0.8 ns ns MAX 210 -- 22 22 MHz ns ns ns UNIT
tsu
th
NOTES: 1. This parameter is not necessarily production tested. 2. Data inputs must be below a minimum time of tact max, after RESET is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken LOW. 4. For data signal input slew rate 1 V/ns. 5. For data signal input slew rate 0.5 V/ns and < 1 V/ns. 6. CK, CK signals input slew rates are 1 V/ns.
2004 Jul 15
7
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
SWITCHING CHARACTERISTICS--PC1600-PC2700
Over recommended operating conditions; Tamb = 0 C to +70 C; VDD = 2.3 V - 2.7 V. Class I, VREF = VTT = VDD x 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS SYMBOL O FROM (INPUT) O TO (OUTPUT) VDD = 2.5 V 0.2 V MIN fmax tpd tpdMSS tPHL CK and CK CK and CK RESET Q Q Q 200 1.1 -- 1.1 MAX -- 2.5 2.9 5 MHz ns ns ns UNIT
SWITCHING CHARACTERISTICS--PC3200
Over recommended operating conditions; Tamb = 0 C to +70 C; VDD = 2.5 V - 2.7 V. Class I, VREF = VTT = VDD x 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS SYMBOL O FROM (INPUT) O TO (OUTPUT) VDD = 2.6 V 0.1 V MIN fmax tpd tpdMSS tPHL CK and CK CK and CK RESET Q Q Q 220 1.1 -- 1.1 MAX -- 1.8 2.1 5 MHz ns ns ns UNIT
PARAMETER MEASUREMENT INFORMATION TEST CIRCUIT
VTT
RL = 50
from output under test
TEST POINT
CL = 30 pF see Note 1
SW02124
Figure 1. Load circuitry NOTE: 1. CL includes probe and jig capacitance.
2004 Jul 15
8
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
AC WAVEFORMS
LVCMOS RESET VDD/2 VDD/2 tact 90% IDD 10% tPHL VDD LVCMOS RESET Input VDD/2 VIL VIH
tinact
SW00752
Waveform 1. Inputs active and inactive times (see Note 1)
Output VTT
VOH
VOL tW VIH INPUT VREF VREF VIL Timing input
SW00755
Waveform 4. Propagation delay times
SW00753
VICR
VI(PP)
Waveform 2. Pulse duration
tsu TIMING INPUT VICR VICR
th VIH
VI(PP) Input VREF VREF
tPLH
tPHL
VIL
VOH VTT VOL
SW00756
Waveform 5. Setup and hold times
OUTPUT
SW00754
Waveform 3. Propagation delay times NOTES: 1. IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. 2. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). 3. The outputs are measured one at a time with one transition per measurement. 4. VTT = VREF = VDD/2 5. VIH = VREF + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 6. VIL = VREF - 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH and tPHL are the same as tpd.
2004 Jul 15
9
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm
SOT684-1
2004 Jul 15
10
Philips Semiconductors
Product data sheet
13-bit 1:2 SSTL_2 registered buffer for DDR
SSTVN16859
REVISION HISTORY
Rev _1 Date 20040715 Description Product data sheet (9397 750 13716)
Data sheet status
Level
I
Data sheet status [1]
Objective data sheet
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data sheet
Qualification
III
Product data sheet
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 07-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 13716
Philips Semiconductors
2004 Jul 15 11

▲Up To Search▲

Price & Availability of SSTVN16859BS

	To Download SSTVN16859BS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .